1. ► CompileTf routines can make use of all the VPI routines.
2. ► Stimulus for simulation must always be in the form of binary data i.e. 0’s and 1’s.
3. ► vpi_scan extracts only one element from iterator as obtained using vpi_iterate.
4. ► Event Driven Simulation will stop if there are no more events.
5. ► vpiSysTfCall returns the handle to the task or function call which occurred in Verilog and in
turn called this C/C++ routine.
6. ► VPI provides routines using which one can easily traverse over design graph.
7. ► Simulation times in VPI are represented two 32bit numbers put together to form a 64bit
8. ► Verilog compiler can detect output mistmatch between Verilog and ‘C’ land when routine is
exported as a function.
9. ► In s_cb_data, the cb_rtn field is used to provide the function pointer which will be called when the callback event happens.
10. ► In C++ callbacks are implemented using object pointers.
11. ► Calling vpi_control(vpiStop) will terminate the simulation.
12. ► SystemVerilog’s Direct Programming Interface is identical to Verilog Procedural Interface,
just that it is more efficient.
13. ► The time used in Event Driven Simulation may not be same as the clock used in the design.
14. ► A checker will typically register itself at cbNextSim time.
15. ► Breadth-first walk on a graph creates a breadth-first tree.