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[All Quizzes] → [Hardware Verification With Verilog and C++] → [Random - All Topics]


1. ► CompileTf routines are called only once for any given function.

A.
B.

2. ► In s_cb_data, the user_data field cannot be NULL.

A.
B.

3. ► vpiSysTfCall returns the handle to the task or function call which occurred in Verilog and in turn called this C/C++ routine.

A.
B.

4. ► Verilog compiler can detect argument mismatch between Verilog and ‘C’ land when a routine is called as a function.

A.
B.

5. ► vpi_scan extracts only one element from iterator as obtained using vpi_iterate.

A.
B.

6. ► Verilog compiler can detect output mistmatch between Verilog and ‘C’ land when routine is exported as a function.

A.
B.

7. ► In C++ callbacks are implemented using object pointers.

A.
B.

8. ► Providing tf.type as vpiSysTask in the s_vpi_systf_data will export the corresponding ‘C’ routine as a task.

A.
B.

9. ► A cbValueChangeCallback is a one-time callback and must be re-registered.

A.
B.

10. ► Verilog Procedural Interface and Programming Language Interface are two entirely distinct Foreign Language Interfaces.

A.
B.

11. ► Foreign Language Interfaces only exist for Hardware Description Languages such as Verilog.

A.
B.

12. ► Callbacks can only be implemented using function pointers in any language.

A.
B.

13. ► BFM stands for Bus Flow Model.

A.
B.

14. ► Bus Monitors only snoop the bus and store the data in easily retrievable form.

A.
B.

15. ► Even Driven Simulation cannot simulate combinational circuits.

A.
B.


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