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[All Quizzes] → [Hardware Verification With Verilog and C++] → [Random - All Topics]


1. ► Calling vpi_control(vpiStop) will terminate the simulation.

A.
B.

2. ► Incorrectly written VPI applications may leak memory.

A.
B.

3. ► BFM stands for Bus Flow Model.

A.
B.

4. ► A cbValueChange callback can be directly registered from vlog_startup_routines called registration function.

A.
B.

5. ► VPI provides routines using which one can easily traverse over design graph.

A.
B.

6. ► Providing tf.type as vpiSysTask in the s_vpi_systf_data will export the corresponding ‘C’ routine as a task.

A.
B.

7. ► Bus Monitors only snoop the bus and store the data in easily retrievable form.

A.
B.

8. ► vpi_scan extracts only one element from iterator as obtained using vpi_iterate.

A.
B.

9. ► Verilog compiler can detect argument mismatch between Verilog and ‘C’ land when a routine is called as a function.

A.
B.

10. ► vpiSysTfCall returns the handle to the task or function call which occurred in Verilog and in turn called this C/C++ routine.

A.
B.

11. ► It is a good practice to have checkers which directly connect to RTL signals in various RTL components.

A.
B.

12. ► CompileTf routines can make use of all the VPI routines.

A.
B.

13. ► There is significant overhead of moving data between simulation and C domains.

A.
B.

14. ► CompileTf routines are called only once for any given function.

A.
B.

15. ► Verilog compiler can detect output mistmatch between Verilog and ‘C’ land when routine is exported as a function.

A.
B.


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