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[All Quizzes] → [Hardware Verification With Verilog and C++] → [Random - All Topics]


1. ► CompileTf routines are called only once for any given function.

A.
B.

2. ► Event Driven Simulation will stop if there are no more events.

A.
B.

3. ► Callbacks can only be implemented using function pointers in any language.

A.
B.

4. ► A cbValueChange callback can be directly registered from vlog_startup_routines called registration function.

A.
B.

5. ► Stimulus for simulation must always be in the form of binary data i.e. 0’s and 1’s.

A.
B.

6. ► Providing tf.type as vpiSysTask in the s_vpi_systf_data will export the corresponding ‘C’ routine as a task.

A.
B.

7. ► CompileTf routines can make use of all the VPI routines.

A.
B.

8. ► Verilog compiler can detect argument mismatch between Verilog and ‘C’ land when a routine is called as a function.

A.
B.

9. ► Calling vpi_control(vpiStop) will terminate the simulation.

A.
B.

10. ► Verilog compiler can detect output mistmatch between Verilog and ‘C’ land when routine is exported as a function.

A.
B.

11. ► Even Driven Simulation cannot simulate combinational circuits.

A.
B.

12. ► Bus Monitors only snoop the bus and store the data in easily retrievable form.

A.
B.

13. ► The time used in Event Driven Simulation may not be same as the clock used in the design.

A.
B.

14. ► Breadth-first walk on a graph creates a breadth-first tree.

A.
B.

15. ► BFM stands for Bus Flow Model.

A.
B.


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