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[All Quizzes] → [Hardware Verification With Verilog and C++] → [Random - All Topics]


1. ► CompileTf routines are called only once for any given function.

A.
B.

2. ► Verilog compiler can detect output mistmatch between Verilog and ā€˜C’ land when routine is exported as a function.

A.
B.

3. ► A cbValueChangeCallback is a one-time callback and must be re-registered.

A.
B.

4. ► vpi_scan extracts only one element from iterator as obtained using vpi_iterate.

A.
B.

5. ► Iterators obtained using vpi_iterate can be rewinded using VPI routines.

A.
B.

6. ► A Verilog design is internally represented in the form of a graph where edges represent the connectivity.

A.
B.

7. ► vlog_startup_routines is a function which is called by simulator to register routines.

A.
B.

8. ► In s_cb_data, the cb_rtn field is used to provide the function pointer which will be called when the callback event happens.

A.
B.

9. ► Simulation times in VPI are represented two 32bit numbers put together to form a 64bit number.

A.
B.

10. ► In s_cb_data, the user_data field cannot be NULL.

A.
B.

11. ► A cbValueChange callback can be directly registered from vlog_startup_routines called registration function.

A.
B.

12. ► It is a good practice to have checkers which directly connect to RTL signals in various RTL components.

A.
B.

13. ► The time used in Event Driven Simulation may not be same as the clock used in the design.

A.
B.

14. ► In s_cb_data, the obj field is used to point to the handle on which the callback is registered.

A.
B.

15. ► Verilog compiler can detect argument mismatch between Verilog and ā€˜C’ land when a routine is called as a function.

A.
B.


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