1. ► Verilog compiler can detect argument mismatch between Verilog and ‘C’ land when a routine is called as a function.
2. ► There is significant overhead of moving data between simulation and C domains.
3. ► CompileTf routines are called only once for any given function.
4. ► All properties are defined for all kinds of handles.
5. ► Verilog compiler can detect output mistmatch between Verilog and ‘C’ land when routine is
exported as a function.
6. ► Depth-first walk is only defined for a Tree.
7. ► Providing tf.type as vpiSysTask in the s_vpi_systf_data will export the corresponding ‘C’ routine as a task.
8. ► Calling vpi_control(vpiStop) will terminate the simulation.
9. ► Callbacks are functions which called by the simulation kernel at appropriate points during
10. ► In C++ callbacks are implemented using object pointers.
11. ► cbReadWriteSync callbacks are called before cbReadOnlySynch callbacks.
12. ► Foreign Language Interfaces only exist for Hardware Description Languages such as Verilog.
13. ► In s_cb_data, the user_data field cannot be NULL.
14. ► VPI programs written on one simulator cannot be ported directly to another simulator.
15. ► The time used in Event Driven Simulation may not be same as the clock used in the design.