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[All Quizzes] → [Hardware Verification With Verilog and C++] → [Random - All Topics]


1. ► cbReadWriteSync callbacks are called before cbReadOnlySynch callbacks.

A.
B.

2. ► Even Driven Simulation cannot simulate combinational circuits.

A.
B.

3. ► In s_cb_data, the cb_rtn field is used to provide the function pointer which will be called when the callback event happens.

A.
B.

4. ► In C++ callbacks are implemented using object pointers.

A.
B.

5. ► Incorrectly written VPI applications may leak memory.

A.
B.

6. ► Depth-first walk is more useful than a breadth-first walk.

A.
B.

7. ► VPI provides routines using which one can easily traverse over design graph.

A.
B.

8. ► vpiSysTfCall returns the handle to the task or function call which occurred in Verilog and in turn called this C/C++ routine.

A.
B.

9. ► Iterators obtained using vpi_iterate can be rewinded using VPI routines.

A.
B.

10. ► Stimulus for simulation must always be in the form of binary data i.e. 0ā€™s and 1ā€™s.

A.
B.

11. ► A Verilog design is internally represented in the form of a graph where edges represent the connectivity.

A.
B.

12. ► In-order depth-first walk is defined for all kinds of trees.

A.
B.

13. ► vlog_startup_routines is a function which is called by simulator to register routines.

A.
B.

14. ► In s_cb_data, the obj field is used to point to the handle on which the callback is registered.

A.
B.

15. ► Verilog compiler can detect output mistmatch between Verilog and ā€˜Cā€™ land when routine is exported as a function.

A.
B.


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