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[All Quizzes] → [Hardware Verification With Verilog and C++] → [Random - All Topics]


1. ► Incorrectly written VPI applications may leak memory.

A.
B.

2. ► It is a good practice to have checkers which directly connect to RTL signals in various RTL components.

A.
B.

3. ► There is significant overhead of moving data between simulation and C domains.

A.
B.

4. ► Providing tf.type as vpiSysTask in the s_vpi_systf_data will export the corresponding ā€˜Cā€™ routine as a task.

A.
B.

5. ► CompileTf routines can make use of all the VPI routines.

A.
B.

6. ► Depth-first walk is only defined for a Tree.

A.
B.

7. ► A cbValueChange callback can be directly registered from vlog_startup_routines called registration function.

A.
B.

8. ► In s_cb_data, the cb_rtn field is used to provide the function pointer which will be called when the callback event happens.

A.
B.

9. ► All properties are defined for all kinds of handles.

A.
B.

10. ► Verilog Procedural Interface and Programming Language Interface are two entirely distinct Foreign Language Interfaces.

A.
B.

11. ► Valgrind can check memory issues with arrays e.g. out of bound access.

A.
B.

12. ► vlog_startup_routines is a function which is called by simulator to register routines.

A.
B.

13. ► cbReadWriteSync callbacks are called before cbReadOnlySynch callbacks.

A.
B.

14. ► In s_cb_data, the obj field is used to point to the handle on which the callback is registered.

A.
B.

15. ► A checker will typically register itself at cbNextSim time.

A.
B.


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