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[All Quizzes] → [Hardware Verification With Verilog and C++] → [Random - All Topics]


1. ► Verilog compiler can detect argument mismatch between Verilog and ‘C’ land when a routine is called as a function.

A.
B.

2. ► There is significant overhead of moving data between simulation and C domains.

A.
B.

3. ► CompileTf routines are called only once for any given function.

A.
B.

4. ► All properties are defined for all kinds of handles.

A.
B.

5. ► Verilog compiler can detect output mistmatch between Verilog and ‘C’ land when routine is exported as a function.

A.
B.

6. ► Depth-first walk is only defined for a Tree.

A.
B.

7. ► Providing tf.type as vpiSysTask in the s_vpi_systf_data will export the corresponding ‘C’ routine as a task.

A.
B.

8. ► Calling vpi_control(vpiStop) will terminate the simulation.

A.
B.

9. ► Callbacks are functions which called by the simulation kernel at appropriate points during simulation.

A.
B.

10. ► In C++ callbacks are implemented using object pointers.

A.
B.

11. ► cbReadWriteSync callbacks are called before cbReadOnlySynch callbacks.

A.
B.

12. ► Foreign Language Interfaces only exist for Hardware Description Languages such as Verilog.

A.
B.

13. ► In s_cb_data, the user_data field cannot be NULL.

A.
B.

14. ► VPI programs written on one simulator cannot be ported directly to another simulator.

A.
B.

15. ► The time used in Event Driven Simulation may not be same as the clock used in the design.

A.
B.


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