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[All Quizzes] → [Hardware Verification With Verilog and C++] → [Introduction to VPI-PLI]


1. ► Even Driven Simulation cannot simulate combinational circuits.

A.
B.

2. ► BFM stands for Bus Flow Model.

A.
B.

3. ► Verilog Procedural Interface and Programming Language Interface are two entirely distinct Foreign Language Interfaces.

A.
B.

4. ► Stimulus for simulation must always be in the form of binary data i.e. 0’s and 1’s.

A.
B.

5. ► The time used in Event Driven Simulation may not be same as the clock used in the design.

A.
B.

6. ► Event Driven Simulation will stop if there are no more events.

A.
B.

7. ► It is a good practice to have checkers which directly connect to RTL signals in various RTL components.

A.
B.

8. ► SystemVerilog’s Direct Programming Interface is identical to Verilog Procedural Interface, just that it is more efficient.

A.
B.

9. ► Foreign Language Interfaces only exist for Hardware Description Languages such as Verilog.

A.
B.

10. ► Bus Monitors only snoop the bus and store the data in easily retrievable form.

A.
B.


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