1. ► It is a good practice to have checkers which directly connect to RTL signals in various RTL components.
2. ► SystemVerilog’s Direct Programming Interface is identical to Verilog Procedural Interface, just that it is more efficient.
3. ► Event Driven Simulation will stop if there are no more events.
4. ► The time used in Event Driven Simulation may not be same as the clock used in the design.
5. ► Even Driven Simulation cannot simulate combinational circuits.
6. ► BFM stands for Bus Flow Model.
7. ► Verilog Procedural Interface and Programming Language Interface are two entirely distinct Foreign Language Interfaces.
8. ► Foreign Language Interfaces only exist for Hardware Description Languages such as Verilog.
9. ► Stimulus for simulation must always be in the form of binary data i.e. 0’s and 1’s.
10. ► Bus Monitors only snoop the bus and store the data in easily retrievable form.
